BACK
Project/Company Name
CUEDA 奇特
Project Leader
Source of Funding/Programme
TSSSU
Description
focus on developing GPU accelerated logic synthesis tools that include a logic equivalence checker and a netlist re-mapper that performs logic optimization and technology mapping with physical information to synthesize an input circuit to netlist with good Performance, Power and Area (PPA) with at least 40 times speedup.
Project/Company Name
CUEDA 奇特
Project Leader
Source of Funding/Programme
TSSSU
Description
focus on developing GPU accelerated logic synthesis tools that include a logic equivalence checker and a netlist re-mapper that performs logic optimization and technology mapping with physical information to synthesize an input circuit to netlist with good Performance, Power and Area (PPA) with at least 40 times speedup.
Starting Year
2025
Business Area
Electrial and Electronics
Nature
TSSSU Company